Researchers at the National Institute of Standards and Technology (NIST) have invented a new approach to testing multilayered, 3D computer chips that are now appearing in some of the latest consumer devices. The method may be the answer the semiconductor industry needs to quickly assess the reliability of this relatively new chip construction model, which stacks layers of flat circuitry atop one another like floors in a building to help make chips ever-faster and packed with features.

The approach overcomes the limitation of conventional chip-testing methods on the so-called 3D chips, which include many thin horizontal “floors” connected to one another by vertical pathways called through-substrate vias, or TSVs. These TSVs are essential to the operation of 3D chips, which have become commercially viable only in the past few years after decades of sustained development effort by the industry.

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